A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a smaller number of outputs, similar to a simple encoder. The output of a priority encoder is the binary representation of the index of the most significant activated line. In contrast to the simple encoder, if two or more inputs to the priority encoder are active at the same time, the input having the highest priority will take precedence. It is an improvement on a simple encoder because it can handle all possible input combinations, but at the cost of extra logic.[1]
Applications of priority encoders include their use in interrupt controllers (to allow some interrupt requests to have higher priority than others), decimal or binary encoding, and analog-to-digital / digital to-analog conversion.[2]
A truth table of a single bit 4-to-2 priority encoder is shown, where the inputs are shown in decreasing order of priority left-to-right, and "x" indicates a don't care term - i.e. any input value there yields the same output since it is superseded by a higher-priority input. The (usually-included) "v" output indicates if the input is valid.
| Input | Output | |||||
| I3 | I2 | I1 | I0 | O1 | O0 | v |
| x | ||||||
| 0 | ||||||
| 0 | ||||||
| 1 | ||||||
| 1 | ||||||
Priority encoders can be easily connected in arrays to make larger encoders, such as one 16-to-4 encoder made from six 4-to-2 priority encoders – four 4-to-2 encoders having the signal source connected to their inputs, and the two remaining encoders take the output of the first four as input.
A priority-encoder, also called leading zero detector (LZD) or leading zero counter (LZC), receives an
n
Priority-encoders can be efficiently constructed by recursion. The input vector is split into
k
n/k
rm{PE}n/k
k
rm{PE}n/k
k
rm{PE}n/k
The depth of the proposed structure is
\lceillogkn\rceil
l{O}(n)
k=4
An open-source Verilog generator for the recursive priority-encoder is available online.[6]
A behavioral description of priority encoder in Verilog is as follows.[6]
module pe_bhv #(parameter OHW = 512) // encoder one-hot input width (input clk, // clock for pipelined priority encoder input rst, // registers reset for pipelined priority encoder input [OHW -1:0] oht, // one-hot input / [OHW -1:0] output reg [`log2(OHW)-1:0] bin, // first '1' index/ [`log2(OHW)-1:0] output reg vld); // binary is valid if one was found // use while loop for non fixed loop length // synthesizable well with Intel's QuartusII always @(*) begin bin = ; vld = oht[bin] ; while ((!vld) && (bin!=(OHW-1))) begin bin = bin + 1 ; vld = oht[bin]; end end
endmodule
See main article: Encoder (digital).
A simple encoder circuit is a one-hot to binary converter. That is, if there are 2n input lines, and at most only one of them will ever be high, the binary code of this 'hot' line is produced on the n-bit output lines.