Back end of line explained

Back end of the line or back end of line (BEOL) is a process in semiconductor device fabrication that consists of depositing metal interconnect layers onto a wafer already patterned with devices. It is the second part of IC fabrication, after front end of line (FEOL). In BEOL, the individual devices (transistors, capacitors, resistors, etc.) are connected to each other according to how the metal wiring is deposited.

Metalization

The individual devices are connected by alternately stacking oxide layers(for insulation purposes) and metal layers (for the interconnect tracks). The vias between layers and the interconnects on the individual layers are thus formed using a structuring process.^[1]

Common metals are copper and aluminum. BEOL generally begins when the first layer of metal is deposited on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. For modern IC processes, more than 10 metal layers can be added in the BEOL.

Before 1998, practically all chips used aluminium for the metal interconnection layers, whereas copper is mostly used nowadays.^[2]

Steps

Steps of the BEOL are:^[3]

1. Silicidation of source and drain regions and the polysilicon region.
2. Adding a dielectric (first, lower layer is pre-metal dielectric (PMD) – to isolate metal from silicon and polysilicon), CMP processing it
3. Make holes in PMD, make a contacts in them.
4. Add metal layer 1
5. Add a second dielectric, called the inter-metal dielectric (IMD)
6. Make vias through dielectric to connect lower metal with higher metal. Vias filled by Metal CVD process.

Repeat steps 4–6 to get all metal layers.

1. Add final passivation layer to protect the microchip

After BEOL there is a "back-end process" (also called post-fab), which is done not in the cleanroom, often by a different company.It includes wafer test, wafer backgrinding, die separation, die tests, IC packaging and final test.

See also

• Front end of line (FEOL)
• Integrated circuit
• Phosphosilicate glass

Further reading

• Book: Silicon VLSI Technology: Fundamentals, Practice, and Modeling. limited. Prentice Hall. 2000. 0-13-085037-3. Chapter 11: Back End Technology. 681–786.
• Book: CMOS: Circuit Design, Layout, and Simulation. Wiley-IEEE. 2010. 978-0-470-88132-3. Chapter 7.2.2: CMOS Process Integration: Backend-of-the-line Integration. 199–208 [177–79].
• "Chapter 2: Technology Know-How: From Silicon to Devices". Fundamentals of Layout Design for Electronic Circuits, by Lienig, Scheible, Springer,, 2020. p. 82 (2.9.4 BEOL: Connecting Devices)

Notes and References

1. Book: J. Lienig, J. Scheible. Fundamentals of Layout Design for Electronic Circuits. 82. Chap. 2.9.4: BEOL: Connecting Devices. Springer. 2020. 10.1007/978-3-030-39284-0. 978-3-030-39284-0. 215840278.
2. Web site: Copper Interconnect Architecture.
3. Book: Handbook of Silicon Wafer Cleaning Technology . 2nd . Karen A. Reinhardt and Werner Kern . William Andrew . 2008 . 978-0-8155-1554-8 . 202 .